`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2024/07/24 16:48:48
// Design Name: 
// Module Name: top
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module top(
    clk,reset_n,addr_ir,data_wb
    );
    
    input clk,reset_n;
    output [31:0] addr_ir;
    output [31:0] data_wb;

    wire nop_b_out,nop_j_out;
    wire [31:0] inst;
    wire [4:0] imm_1;
    wire [11:0] imm_2;
    wire [6:0] imm_3;
    wire [19:0] imm_4;
    wire [4:0] rd_id,rd_exe,rd_mem,rd_wb,rd_exe_fw,rd_mem_fw,rd_wb_fw;
    wire [31:0] data_exe,data_mem,data_2_exe,data;
    wire [6:0] opcode_id,opcode_exe;
    wire lu,nop_fw;
    wire [1:0] fw_1,fw_2;

    wire [31:0] data_1,data_2;
    wire [31:0] sex_imm,sex_imm_b,sex_imm_b_mem;
    wire zero,zero_mem;
    wire [31:0] data_fw_1,data_fw_2;

    wire [2:0] op_imm;
    wire [1:0] op_wr,op_wr_exe;
    wire [1:0] op_rd,op_rd_exe,op_rd_mem;
    wire op_j,op_b,op_j_exe,op_b_exe,op_b_mem;
    wire [2:0] op_alu;

    wire [31:0] addr_next,addr_next_id,addr_next_if,addr_next_exe,addr_next_mem;

    inst_fetch inst_fetch(.clk(clk),.reset_n(reset_n),.addr(addr_ir),.addr_ir(addr_ir),.inst(inst),.op_b_mem(op_b_mem),
    .op_j_exe(op_j_exe),.addr_next(addr_next),.offset_j(sex_imm),.offset_b_mem(sex_imm_b_mem),.zero_mem(zero_mem),
    .nop_b_out(nop_b_out),.nop_j_out(nop_j_out),.lu(lu),.nop_b(nop_b_out),.nop_j(nop_j),.nop_fw(nop_fw),.addr_next_id(addr_next_id),
    .addr_next_exe(addr_next_exe));
    inst_decode inst_decode(.clk(clk),.reset_n(reset_n),.nop_j(nop_j_out),.nop_b(nop_b_out),.inst(inst),.rd_wb(rd_wb),.data_wb(data_wb),
    .op_imm(op_imm),.data_1(data_1),.data_2(data_2),.imm_1(imm_1),.imm_2(imm_2),.imm_3(imm_3),.imm_4(imm_4),.rd_id(rd_id),
    .op_wr(op_wr),.op_rd(op_rd),.op_rd_mem(op_rd_mem),.op_b(op_b),.op_j(op_j),.addr_next_if(addr_next),.addr_next_id(addr_next_id),
    .op_alu(op_alu),.opcode_id(opcode_id),.opcode_exe(opcode_exe),.lu(lu),.fw_1(fw_1),.fw_2(fw_2),.rd_exe_fw(rd_exe_fw),.rd_mem_fw(rd_mem_fw),
    .nop_fw(nop_fw));
    execute execute(.clk(clk),.nop_b(nop_b_out),.data_1(data_1),.data_2(data_2),.rd_id(rd_id),.op_imm(op_imm),
    .imm_1(imm_1),.imm_2(imm_2),.imm_3(imm_3),.imm_4(imm_4),.zero(zero),.data_exe(data_exe),.rd_exe(rd_exe),.data_2_exe(data_2_exe),
    .op_wr_id(op_wr),.op_wr_exe(op_wr_exe),.op_rd_id(op_rd),.op_rd_exe(op_rd_exe),.op_j_id(op_j),.op_b_id(op_b),.op_j_exe(op_j_exe),
    .op_b_exe(op_b_exe),.op_alu(op_alu),.addr_next_id(addr_next_id),.addr_next_exe(addr_next_exe),.sex_imm(sex_imm),.sex_imm_b(sex_imm_b),
    .opcode_id(opcode_id),.opcode_exe(opcode_exe),.fw_1(fw_1),.fw_2(fw_2),.data_fw_1(data_fw_1),.data_fw_2(data_fw_2),.rd_exe_fw(rd_exe_fw));
    mem mem(.clk(clk),.reset_n(reset_n),.rd_exe(rd_exe),.addr(data_exe),.data_2_exe(data_2_exe),.rd_mem(rd_mem),.data_mem(data_mem),
    .op_wr_exe(op_wr_exe),.op_rd_exe(op_rd_exe),.op_rd_mem(op_rd_mem),.data(data),.addr_next_exe(addr_next_exe),.addr_next_mem(addr_next_mem),
    .zero_exe(zero),.zero_mem(zero_mem),.op_b_exe(op_b_exe),.op_b_mem(op_b_mem),.sex_imm_b_exe(sex_imm_b),.sex_imm_b_mem(sex_imm_b_mem),
    .data_fw_1(data_fw_1),.rd_mem_fw(rd_mem_fw));
    wb wb(.clk(clk),.rd_mem(rd_mem),.data(data),.data_mem(data_mem),.rd_wb(rd_wb),.data_wb(data_wb),.op_rd_mem(op_rd_mem),
    .addr_next_mem(addr_next_mem),.data_fw_2(data_fw_2));
endmodule
